Product Summary
The IP1000A is a truly 10/100/1000Mbps Gigabit Ethernet NIC single chip which it incorporates a 32-bit PCI interface wit bus master support. The IP1000A is manufactured using standard digital CMOS process and contain all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT5 unshielded twisted pair cable.
Features
IP1000A features: (1)PCI Specification Revision 2.3 compliant; (2)32-bit, 33/66MHz bus master capability; (3)Efficient DMA operation maximizes PCI band-width utilization; (4)1 Terabyte (40 bit) address space; (5)Scatter, gather transmit/receive DMA; (6)Receive frame priority interrupts; (7)Receive interrupt; (8)Receive interrupt coalescing.
Diagrams
IP1001 |
IC REG BUCK SYNC ADJ 20A 256BGA |
Data Sheet |
Negotiable |
|
||||||
IP1001LF |
Other |
Data Sheet |
Negotiable |
|
||||||
IP1001TR |
IC REG BUCK SYNC ADJ 20A 256BGA |
Data Sheet |
Negotiable |
|
||||||
IP101 |
Other |
Data Sheet |
Negotiable |
|
||||||
IP101ALF |
Other |
Data Sheet |
Negotiable |
|
||||||
IP102 |
Other |
Data Sheet |
Negotiable |
|