(China (Mainland))
Product Summary
The XC2S150-5PQG208I is a Field-Programmable Gate Array. The XC2S150-5PQG208I gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The XC2S150-5PQG208I offers densities ranging from 15,000 to 200,000 system gates. System performance is supported up to 200 MHz. Features of the XC2S150-5PQG208I include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The XC2S150-5PQG208I is a superior alternative to mask-programmed ASICs.
Parametrics
XC2S150-5PQG208I absolute maximum ratings: (1)VCCINT, Supply voltage relative to GND: –0.5 to 3.0 V; (2)VCCO, Supply voltage relative to GND: –0.5 to 4.0 V; (3)VREF, Input reference voltage: –0.5 to 3.6 V; (4)VIN, Input voltage relative to GND: 5V tolerant I/O: –0.5 to 5.5V; No 5V tolerance:–0.5 VCCO+0.5 V; (5)VTS, Voltage applied to 3-state output, 5V tolerant I/O: –0.5 to 5.5 V; No 5V tolerance: –0.5 to VCCO+0.5 V; (6)TSTG, Storage temperature (ambient): –65 to +150℃; (7)TJ, Junction temperature: +125℃.
Features
XC2S150-5PQG208I features: (1)Densities as high as 5,292 logic cells with up to 200,000 system gates; (2)Streamlined features based on Virtex FPGA architecture; (3)Unlimited reprogrammability; (4)Very low cost; (5)Cost-effective 0.18 micron process; (6)Fully PCI compliant; (7)Low-power segmented routing architecture; (8)Full readback ability for verification/observability; (9)Dedicated carry logic for high-speed arithmetic; (10)Efficient multiplier support; (11)Cascade chain for wide-input functions; (12)Abundant registers/latches with enable, set, reset; (13)Four dedicated DLLs for advanced clock control; (14)Four primary low-skew global clock distribution nets.
Diagrams
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